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| PHYSICAL LAYER PRODUCT ETHERNET PRODUCT VSC7323 VSC7323 Meigs-IIeTM - 10 x 1G and 10G Ethernet MAC Chip S P E C I F I C AT I O N S : Implemented in low Power 0.18 micron CMOS Technology, 2.5V/3.3V IO Industrial Temperature Range (-40C to +85C) Standard 5-Pin P1149.1 JTAG Test Port Packaged in a 728 pin TBGA A P P L I C AT I O N S : Enterprise and Metro Ethernet Switches Multi-Service Provisioning Platforms F E AT U R E S : Ten Triple-Speed Ethernet MACs w/Support for RGMII/GMII/MII Integrated GbE SERDES for Direct Connection to Optical Modules Intelligent VLAN and MPLS Identification Loss less flow Control in Metro Applications up to 10km 10GbE MAC w/Integrated XAUI SERDES Interface Compliant to IEEE 802.3ae Low Pin Count, low Power OIF SPI-4.2 System Interface PHY Metro SONET/SDH Transport (ADMs) Edge and Core Aggregation Routers DWDM Transport Terminals (Wavelength Routers) A P P L I C AT I O N D I A G R A M S : 10 x GbE MAC interfacing to NPU or ASIC 10 x GbE MAC w/ RGMII/GMII PHY VSC7323 NPU or ASIC Switch or Transceiver Extensive Loopback Capabilities for Both Line and System Side RGMII/GMII SPI-4.2 Backplane or Switch Interface Configurable Parallel or Serial CPU Interface 10 x GbE over SONET/SDH using the VSC9118 Dual MIIM Interface for Managing PHY Devices Independent Egress and Ingress Shaping/Policing Rate Limiting in 1 Mb/s Increments 802.3ad Compliant Link Aggregation and Trunking Statistical Support for RMON 1 (RFC2819), IEEE 802.3 Annex 30A, and SNMP (RFC 1213, 1573, and 1643) Supports Both Minimum Size 64B Frames as well as 9600B Jumbo Frames Automatic Generation of PAUSE Frames Based on Programmable Per Port FIFO Watermarks O/E O/E O/E 10 x GbE MAC w/ Integrated Serdes Packet Mapper with VC and GFP STS-1 Grooming TSI VSC7323 VSC9118 VSC9185 Serial SPI-4.2 Backplane Interface 10 GbE MAC interfacing to NPU or ASIC 10 GbE MAC w/ Integrated XAUI VSC7323 NPU or ASIC SPI-4.2 Switch or Transceiver XAUI Backplane or Switch Interface Enterprise Access Metro Core PB-VSC7323-001 VSC7323 VSC7323 Meigs-IIeTM - 10 x 1G and 10G Ethernet MAC Chip GENERAL DESCRIPTION: The VSC7323 (MeigsTM-IIe) is a versatile building block for a range of high-density Gigabit Ethernet (GbE) and 10GbE applications within the Enterprise, Metro, and Core. The VSC7323 integrates 10 triple-speed MACs with integrated SerDes, a single 10 Gigabit Ethernet (GbE) MAC with an integrated 10 Gigabit Attachment Unit Interface (XAUI), an OIF-compliant SPI-4.2 interface, a configurable parallel/serial CPU interface, and dual MII Management interface. Interfacing to the triple-speed MAC ports is accomplished using MII for 10/100 Ethernet support and RGMII/GMII for GbE support. The integrated GbE SerDes enables high density, costefficient per port pricing for Ethernet aggregation services. The full duplex, IEEE 802.3ae-compliant 10GbE MAC performs pad insertion to ensure minimum frame length and CRC generation as well as preamble, SFD, and IFG insertion on transmit. On the receive side, the 10GbE MAC performs Ethernet framing, CRC validation, and length monitoring. The VSC7323 connects seamlessly to 10 Gb/s optical modules such as XENPAK, X2, and XPAK using the integrated XAUIcompliant serial interface. The quad lane 3.125 Gb/s interface implements programmable pre-emphasis on transmit to compensate for inter-symbol interference (ISI) and equalization on receive to ensure reliability in high loss, high distortion environments. The internal ingress (Rx) and egress (Tx) FIFOs, which are provisionable on a per port basis in increments of 2 kB, are capable of handling short-haul flow control and accommodating bursty traffic between the Ethernet MACs and the SPI-4.2 system interface. The FIFO structures are independently configurable for either cut-through or storeand-forward modes. The system side of the VSC7323, an industry standard OIF SPI-4.2 interface, is used to seamlessly transfer packet date between the VSC7323 and other devices such as network processors, SONET/SDH mappers, and customer ASICs. The 16-bit SPI-4.2 interface can transmit (ingress) data at 312.5/390.625 MHz DDR and receive (egress) data in the range of 311 to 450 MHz DDR. The CPU interface can be configured as either a parallel interface for seamless connection to PowerPCTM and IntelTM microprocessors or as a simple 4-line serial interface for device initialization, control register, and per port statistic access. The VSC7323 also integrates two MII Management (MIIM) interfaces for managing and gathering status from the PHY devices. The VSC7323 is an ideal solution for OEMs designing 10 Gb/s or higher solutions that require GbE and 10GbE support. The VSC7323 also provides a seamless solution for frame-mapped (GFP-F) Ethernet-over-SONET/SDH applications when used in conjunction with Vitesse's VSC9118, a 10 Gb/s SONET/SDH VC & GFP Mapper. BLOCK DIAGRAM: Quad Serial 3.125 GHz XAUI Interface Aggregation MIIM VSC7323 10GbE MAC Ingress (Rx) FIFO SERDES or RGMII GMII/MII Tri-speed MAC Ten Ports 10/100/1000 Mbps Port #0 Port # 9 Egress (Tx) FIFO Statistics 16-bit Parallel or 4-bit Serial CPU Interface JTAG Port For more information on Vitesse Products visit the Vitesse web site at www.vitesse.com or contact Vitesse Sales at (800) VITESSE or sales@vitesse.com 741 Calle Plano Camarillo, CA 93012, USA Tel: +1 805.388.3700 Fax: +1 805.987.5896 www.vitesse.com (c)2003 Vitesse Semiconductor Corporation 16 bit SPI-4.2 System Interface |
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